1. Field of the Invention
The field of art to which this invention relates is the fabrication of semiconductor printed circuit boards. It is more particularly directed to drilling of multi layer printed circuit boards.
2. Description of Prior Art
Multi layer circuit boards are becoming increasingly more difficult to manufacture due to a continuing push toward greater functionality and increased wireability by shrinking line widths, line spacing, pad sizes, and drilled hole diameters. This increased density and complexity has placed greater demand on the ability of manufacturers to reduce registration tolerances.
In particular, a complex circuit board may be fabricated from a dozen or more individual circuitized cores which are stacked with dielectric in between and laminated together under heat and pressure. The alignment of these cores to each other and dimensional changes that occur during the core fabrication and under the heat and the pressure of the lamination, can result in significant misregistration of cores to each other and to their nominal or presumed location.
After lamination, holes are typically drilled and copper plated to form connections to desired inner layer circuits while avoiding connections to nearby undesired printed circuitry. Not only must the drill avoid any contact with an inner circuit where no connection is desired, it must also stay a safe distance away from those inner circuits, so that over years of use a conductive growth does not form to cause an electrical short. The dielectric immediately surrounding the drilled holes may be slightly damaged or fractured by drilling and a chemical attack, or the dielectric may have been slightly imperfect to begin with, necessitating a few thousandth of an inch safety margin.
It is thus a goal of circuit board manufacturer's to minimize the variability of the inner layer registration so that uniform drilling can be accomplished through all the through holes at their predetermined print locations. To achieve this goal, a method is sometimes employed to drill the first panel in a lot, get a general feel for errors between drilled holes and inner layers by looking at the panel with x-ray, and then drill the rest of the lot after making the correction determined from the x-ray picture of the first panel.
An improved method involves drilling a few holes in test areas and then looking at the panel with x-ray. In this procedure some information is gained prior to committing any panels to possible scrap.
Current methods for adjusting drilling for panel misregistrations involve inspecting every panel and adjusting the drills for every panel to match its particular misregistration. One such method is described in the U.S. Pat. No. 5,529,441 (Kosmowski et al.). Kosmowski et al. uses a beveled drill to gain optical access to inner layer targets, which are looked at and used to adjust the panel's position before drilling. The drawback of this method however, is the apparent inability to cleanly perform the bevel cut without smearing the inner layer of copper, and to get a good optical image to accurately measure the location of the revealed inner layer features, especially when those inner layer features are thin.
Furthermore, a regression fit of the location data gathered to optimize the panel position is used. The regression fit minimizes the sum of the squares of all the errors in the location data. If one layer among many is distinctly different from the rest, its errors are diluted by being averaged with all the other layers and the optimized panel position is not at all optimal for the rogue layer. If any of the layers are too misregistered and out of specification, the panel will be scrapped, so accommodating the majority of the layers while giving little aid to the worst layer will often result in scrap.
A second such method is described in the U.S. Pat. No. 4,790,694 (Wilent et al.). Wilent et al. uses overlapping targets on the internal planes. An X-ray is used to look at these targets, and the panel is translated and rotated and a new location system is formed in relation to these targets. Drilling is then performed conventionally with the panel pinned in registration to the new location system. The drawback with this method is that the reduction of error is decreased by the tolerance involved in creating the new location system. Additionally, layer to layer and panel to panel variation in scale i.e., shrinkage can be of similar magnitude to variation in the XY position and rotation. The panel shrinkage is not taken into account when the optimal translation and rotation are calculated. One corner of an inner layer in the board, which appears to be the worst registered and therefore heavily weighted in the optimization process would in fact turn out to be well registered and not a critical point of interest when shrinkage is also optimized. Whatever method is employed reducing such misregistrations, will remove a major impediment to further increasing circuit density, increasing wireability of designs, and decrease scrap waste, therefore it is of a significant interest to the printed circuit industry.